CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
6.5 Control — PME_CXT
Register Name: Control — PME_CXT
Memory Offset: 010h
Bit 31
Bit 30
Bit 29
Byte 3
Byte 2
Bit 23
Bit 22
Bit 21
Byte 1
Bit 15
Bit 14
Bit 13
Byte 0
Bit 7
Stop Clock
R/W:0
Bit 6
Bit 5
VCC Control
R/W:000
Bit 28
Bit 27
Reserved
R:00000000
Bit 20
Bit 19
Reserved
R:00000000
Bit 12
Bit 11
Reserved
R:00000000
Bit 4
Bit 3
Reserved
R:0
Bit 26
Register Per: socket
Bit 25
Bit 24
Bit 18
Bit 17
Bit 16
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VPP Control
R/W:000
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 by a software PCI Bus Segment reset.
The Socket Control register provides control of the socket’s VCC and VPP. All bits in this register are set
to ‘0’ by RST# and power removed from the socket. This register is write-protected by writes to bits 13:10
of the Event Force register, and not write-protected on completion of the decoding sequence of the CD1,
CD2, VS1, and VS2 lines or completion of CV test. Use either this register or the Power Control register
(index 02h) for power control. Do not use both registers.
Bits 2:0 — VPP Control
These bits are used to switch the VPP power using external VPP control logic. The CL-PD6833 has
no knowledge of a card’s VPP voltage requirement. Software must determine the needed voltage
from the card’s CIS. The following table shows the VPP requested depending on the setting of the
bits.
Bit 2
0
0
0
0
Bit 1
0
0
1
1
100—111
Bit 0
0
1
0
1
VPP Requested
0V
12.0 V
5.0 V
3.3 V
Reserved
82
CARDBUS REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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