CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PD6833-QC-A

PCI-to-CardBus Host Adapter

Cirrus Logic 

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CL-PD6833

PCI-to-CardBus Host Adapter

Table 7-1. Index Registers (cont.)

Register Name

Gen Map 5 Offset Address Low

Gen Map 5 Offset Address High

Gen Map 6 Offset Address Low

Gen Map 6 Offset Address High

Setup Timing 0

Command Timing 0

Recovery Timing 0

Setup Timing 1

Command Timing 1

Recovery Timing 1

Reserved

Reserved

Reserved

Scratchpad

Reserved

Reserved

I/O Index Value

Six-bit Value

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

a This register affects both sockets (it is not specific to either socket).

Memory

Offset Value

836h

837h

838h

839h

83Ah

83Bh

83Ch

83Dh

83Eh

83Fh

905h–909h

916h–917h

920h–921h

90Ch–913h

847h–8FFh

93Ch–FFFh

Chapter

Chapter 10,

“GENERAL

WINDOW

MAPPING

REGISTERS”

Chapter 12,

“TIMING

REGISTERS”

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Page

123

124

123

124

167

168

169

167

168

169

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June 1998

ADVANCE DATA BOOK v0.3

89

OPERATION REGISTERS

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