CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
8.7 Mapping Enable
Register Name: Mapping Enable
I/O Index: 06h
Memory Offset: 806h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Map 1
Enable
I/O Map 0
Enable
Compatibility
Memory Map
4 Enable
Memory Map
3 Enable
Memory Map
2 Enable
Memory Map
1 Enable
Memory Map
0 Enable
R/W:0
R/W:0
R:0
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
Bit 0 — Memory Map 0 Enable
0
Memory Window Mapping registers for Memory Window 0 disabled.
1
Memory Window Mapping registers for Memory Window 0 enabled.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 0 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Bit 1 — Memory Map 1 Enable
0
Memory Window Mapping registers for Memory Window 1 disabled.
1
Memory Window Mapping registers for Memory Window 1 enabled.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 1 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Bit 2 — Memory Map 2 Enable
0
Memory Window Mapping registers for Memory Window 2 disabled.
1
Memory Window Mapping registers for Memory Window 2 enabled.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 2 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Bit 3 — Memory Map 3 Enable
0
Memory Window Mapping registers for Memory Window 3 disabled.
1
Memory Window Mapping registers for Memory Window 3 enabled.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 3 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Bit 4 — Memory Map 4 Enable
0
Memory Window Mapping registers for Memory Window 4 disabled.
1
Memory Window Mapping registers for Memory Window 4 enabled.
When this bit is ‘1’, the Memory Window Mapping registers for Memory Window 4 are enabled
and the controller responds to memory accesses in the memory space defined by those registers.
Bit 5 — Compatibility Bit
June 1998
ADVANCE DATA BOOK v0.3
DEVICE CONTROL REGISTERS
101
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