CL-PS7110
Low-Power System-on-a-Chip
Table 2-2. Numeric Pin Listinga (cont.)
Pin
No.
Signal
Bufferb
Reset
and Pin
Test
Rest
State
55
EINT[3]
–
Input
56
NEINT[2]
–
Low
57
NEINT[1]
–
Low
58
NEXTFIQ
–
Low
59 PE[1]/NIRQ I/O - strength 1
I/O
60
PE[1]/
BOOTSEL
I/O - strength 1
I/O
61
PD[7]
I/O - strength 3
Low
62
PD[6]
I/O - strength 3
Low
63
PD[5]
I/O - strength 3
Low
64
PD[4]
I/O - strength 3
Low
65
VDD
Pad power
–
66
VSS
Pad power
–
67
PD[3]
I/O - strength 1
Low
68
PD[2]
I/O - strength 1
Low
69
PD[1]
I/O - strength 1
Low
70
PD[0]
I/O - strength 1
Low
71
PCMIN
I/O - strength 1
Input
72
PCMCK
I/O - strength 1
Low
73
PCMOUT I/O - strength 1
Low
74
PCMSYNC I/O - strength 1
Low
75
ADCIN
I/O - strength 1
Input
76
NADCCS I/O - strength 1
High
77
VSS
Core power
–
78
VDD
Core power
–
79
VSS
Pad power
–
80
VDD
Pad power
–
81
DRIVE[1]
I/O - strength 4 High/Low
Table 2-2. Numeric Pin Listinga (cont.)
Pin
No.
Signal
Bufferb
Reset
and Pin
Test
Rest
State
82
DRIVE[0]
I/O - strength 4 High/Low
83
ADCCLK
I/O - strength 1
Low
84
ADCOUT I/O - strength 1
Low
85
SMPLCK
I/O - strength 1
Low
86
FB1
I/O - strength 1
Input
87
FB0
I/O - strength 1
Input
88
COL[7]/
PTOUT
I/O - strength 1
High
89
COL[6]
I/O - strength 1
High
90
COL[5]
I/O - strength 1
High
91
COL[4]
I/O - strength 1
High
92
COL[3]
I/O - strength 1
High
93
COL[2]
I/O - strength 1
High
94
VDD
Pad power
–
95
VSS
Pad power
–
96
COL[1]
I/O - strength 1
High
97
COL[0]
I/O - strength 1
High
98
BUZ
I/O - strength 1
Low
99
D[31]
I/O - strength 1
Low
100
D[30]
I/O - strength 1
Low
101
D[29]
I/O - strength 1
Low
102
D[28]
I/O - strength 1
Low
103
A[27]
I/O - strength 1
Low
104 A[27]/DRA[0] I/O - strength 2
Low
105 A[26]/DRA[1] I/O - strength 2
Low
106
D[26]
I/O - strength 1
Low
107 A[25]/DRA[2] I/O - strength 1
Low
108
D[25]
I/O - strength 1
Low
36
PIN INFORMATION
May 1997
DATA BOOK v1.5