CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
ADCKSEL
Microwire®/SPI® peripheral clock speed select. This 2-bit field selects the frequency
of the ADC sample clock, which is twice the frequency of the synchronous serial ADC
interface clock. Table 3-5 shows the available frequencies.
Table 3-5. ADCCLK Frequencies
ADCKSEL
00
01
10
11
ADC Sample frequency (kHz) —
SMPCLK
8
32
128
256
ADC interface frequency (kHz) —
ADCCLK
4
16
64
128
WAKEDIS
IRTXM
Bits 21–23
If this bit is set, switch-on (through the wake-up input) is disabled.
IrDA Tx mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means
each ‘0’ bit transmitted is represented as a pulse of width 3/16th of the bit rate period.
Setting this bit means each ‘0’ bit is represented as a pulse of width 3/16th of the
period of 115,000 bit rate clock, that is, 1.6 µs, regardless of the selected bit rate. Set-
ting this bit reduces power consumption, but probably reduces transmission dis-
tances.
Reserved. Write has no effect, always reads ‘0’.
3.2.12 SYSFLG — System Status Flags Register
The System Status Flags register is a 32-bit read-only register that indicates various system information.
The bits in this register are defined in Table 3-6.
Table 3-6. Bits in the System Status Flags Register
7
DID
15
14
CLDFLG
PFFLG
23
22
UTXFF
URXFE
31
30
VERID
4
3
2
1
WUON
WUDR
DCDET
13
12
11
10
9
RSTFLG NBFLG
UBUSY
DCD
DSR
21
16
RTCDIV
29
28
27
26
25
Reserved Reserved BOOT8BIT SSIBUSY CTXFF
0
MCDR
8
CTS
24
CRXFE
May 1997
DATA BOOK v1.5
45
PROGRAMMING INTERFACE
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