CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
MCDR
DCDET
WUDR
WUON
DID
CTS
DSR
DCD
UBUSY
NBFLG
RSTFLG
PFFLG
CLDFLG
RTCDIV
URXFE
UTXFF
Media changed direct read. This bit reflects the non-latched status of the media
changed input.
This bit is set if the main adapter is powering the system (the inverted state of the
NDCDET input pin).
Wake-up direct read. This bit reflects the non-latched state of the wake-up signal.
This bit is set if the system is brought out of standby by a rising edge on the wake-up
signal. It is cleared by a system reset or by writing to the HALT or STDBY locations.
Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines.
The state of the four LCD data lines is latched by the LCDEN bit and will always reflect
the last state of these lines before the LCD controller was enabled. These bits identify
the LCD display panel.
This bit reflects the current status of the clear to send (CTS) modem-control input to
the built-in UART.
This bit reflects the current status of the data set ready (DSR) modem control input
to the built-in UART.
This bit reflects the current status of the data carrier detect (DCD) modem control
input to the built in UART.
UART transmitter busy. This bit is set while the internal UART is busy transmitting
data, it is guaranteed to remain set until the complete byte has been sent, including
all stop bits.
New battery flag. This bit is set if a low-to-high transition has occurred on the
NBATCHG input; it is cleared by writing to the STFCLR location.
Reset flag. This bit is set if the RESET button is pressed, forcing the NURESET input
low. It is cleared by writing to the STFCLR location.
Power fail flag. This bit is set if the system has been reset by the power fail input pin,
it is cleared by writing to the STFCLR location.
Cold start flag. This bit is set if the CL-PS7110 has been reset with a power on reset;
it is cleared by writing to the STFCLR location.
This 6-bit field reflects the number of 64-Hz ticks that have passed since the last
increment of the RTC. It is the output of the divide-by-64 chain that divides the 64-Hz
tick clock down to 1 Hz for the RTC. The MSB is the 32-Hz output, the LSB is the 1-
Hz output.
UART receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART Bit Rate and Line Control register. If the FIFO is disabled, this
bit is set when the Rx Holding register is empty. If the FIFO is enabled the URXFE bit
is set when the Rx FIFO is empty.
UART transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART Bit Rate and Line Control register. If the FIFO is disabled, this
bit is set when the Tx Holding register is full. If the FIFO is enabled the UTXFF bit is
set when the Tx FIFO is full.
46
PROGRAMMING INTERFACE
May 1997
DATA BOOK v1.5
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