CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 1-1. Interrupt Allocation
Interrupt
FIQ
FIQ
FIQ
FIQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
Bit in Mask
and ISR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
Comment
EXTFIQ
BLINT
WEINT
MCINT
CSINT
EINT1
EINT2
EINT3
TC1OI
TC2OI
RTCMI
TINT
UTXINT
URXINT
UMSINT
SSEOTI
External fast interrupt input (NEXTFIQ pin).
Battery low interrupt.
Watch dog expired interrupt.
Media changed interrupt.
Codec sound interrupt.
External interrupt input 1 (NEINT1 pin).
External interrupt input 2 (NEINT2 pin).
External interrupt input 3 (EINT3 pin).
TC1 under flow interrupt.
TC2 under flow interrupt.
RTC compare match interrupt.
64-Hz tick interrupt.
Internal UART transmit FIFO empty interrupt.
Internal UART receive FIFO full interrupt.
Internal UART modem status changed interrupt.
Synchronous serial interface end of transfer interrupt.
1.2.4 Memory Interface and DMA
The CL-PS7110 memory controller is designed for maximum flexibility. Requests for external memory
accesses from the ARM710A are decoded and the appropriate external memory access or internal bus
cycle is initiated accordingly.
There are two main external memory interfaces:
q DRAM controller
q Expansion memory controller for SRAM/FLASH/ROM
The CL-PS7110 provides a DMA controller (see Section 1.2.5) that allows video display data for the LCD
controller to be fetched directly from main DRAM memory, independent of internal CL-PS7110 activity.
Bus cycles generated by the CL-PS7110 depend on the requester and the target. The possible requesters
are the ARM710A core, the DMA controller and the DRAM refresh controller. The two types of targets are
DRAM banks and ROM/expansion banks. A data transfer may take multiple bus cycles. The arbitration for
the bus is at the beginning of a transfer. The priority is fixed with DMA highest, then refresh, followed by
the ARM710A. Once granted the bus, the maximum burst to a ROM/expansion bank is four bus cycles,
regardless of the transfer width. The ARM710A core can produce byte, word, multi-word accesses. Multi-
14
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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