CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
The DRAM controller contains a programmable refresh counter. The refresh rate is controlled using the
DRAM Refresh Period register (DRFPR).
1.2.8 Codec Interface
The codec interface allows a direct connection of a telephony-type codec to the CL-PS7110. It provides
all the necessary clocks and timing pulses and performs serialization of the data stream (or vice versa)
to or from the codec. The interface is full-duplex and contains two separate data FIFOs.
Data is transferred to or from the codec at 64 kbps, either written to or read from the appropriate 16-byte
FIFO. The sound interrupt is generated every 8 bytes transferred (FIFO half full/empty), which means the
interrupt rate is reduced from 8 to 1 kHz with a latency of 1 ms.
1.2.9 Synchronous Serial Interface
The synchronous serial interface allows peripheral devices, such as ADCs, that have a SPI- or Microwire-
compatible interface to be directly connected to the CL-PS7110. The clock output frequency (ADCCLK)
is programmable and only active during data transmissions to save power (refer to the Example 1 table
on page 24). The output channel is fed by an 8-bit shift register, and the input channel is captured by a
16-bit shift register. The clock and synchronization pulses are activated by a write to the Output Shift reg-
ister. During transfers the SSIBUSY (Synchronous Serial Interface Busy) bit in the System Status Flags
register is set. When the transfer is complete and valid data is in the 16-bit read shift register the SSEOTI
interrupt is asserted and the SSIBUSY bit is cleared. An additional sample clock (SMPCLK) can be
enabled independently and is set at twice the transfer clock frequency.
1.2.10 LCD Controller
The LCD controller provides all necessary control signals to directly interface to a single-scan panel mul-
tiplexed LCD. The panel size is programmable and can be any width (line length) from 16 to 1024 pixels
in 16-pixel increments. The total video frame size is programmable up to 128 Kbytes. This equates to a
theoretical maximum panel size of 1024 × 256 pixels in 4-bits-per-pixel mode. The LCD controller uses a
9-stage FIFO to buffer the incoming display data, which is replenished by hardware DMA under the control
of the CL-PS7110 DMA controller.
The video RAM is mapped into the base of the main DRAM memory area, which is fixed at physical
address 0xC000.0000. The number of bits per pixel is programmable from 1, 2, or 4.
The screen is mapped to the video buffer as one contiguous block where each horizontal line of pixels is
mapped to a set of consecutive bytes or words in the video RAM. The video buffer can be accessed word-
wide as pixel 0 is mapped to the LSB in the buffer, that is, the pixels are arranged in a little-endian manner.
The pixel bit rate and the LCD refresh rate can be programmed from 18.432 MHz to 576 kHz. The LCD
controller is programmed by writing to the LCD Control register (LCDCON).
The LCD controller also contains two 32-bit palette registers, these allow any 4-, 2-, or 1-bit pixel value to
be mapped to any of the 15 grayscale values available. Any 4-bit logical grayscale value can be mapped
to any of the 16 physical grayscales. The palettes are written to directly as two 32-bit memory-mapped
registers.
Figure 1-5 on page 22 shows the organization of the video map for all combinations of bits per pixel.
May 1997
DATA BOOK v1.5
21
FUNCTIONAL DESCRIPTION
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