CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
UART operation and line speed are controlled by the UART Bit Rate and Line Control (UBRLCR) register.
Three interrupts can be generated by the UART: Rx, Tx, and Modem Status Changed. The Rx interrupt
is asserted when the FIFO becomes half full or if the FIFO is non-empty for longer than three character
length times with no more characters being received. The Tx interrupt is asserted if the FIFO buffer
reaches half empty. The Modem Status Changed interrupt is generated if either of the modem status bits
change state.
Framing and parity errors are detected as each byte is received and pushed onto the Rx FIFO. An overrun
error generates an Rx interrupt immediately. All error bits can be read from the 11-bit-wide data register.
The FIFO can also be programmed to only be 1 byte deep (such as, a conventional UART with double
buffering).
The CL-PS7110 also contains an IrDA SIR protocol encoder. This encoder can be optionally switched into
the Tx and Rx signals, so that these can be used to directly drive an infrared interface. If the SIR protocol
encoder is enabled, the UART Tx line is held in the passive state and transitions of the Modem Status
Changed or Rx lines have no effect.
1.2.12 Timer Counters
The CL-PS7110 has two integrated identical timer counters, referred to as TC1 and TC2. Each timer
counter has an associated 16-bit read/write data register and some control bits in the System Control reg-
ister. Each counter is immediately loaded with the value written to the data register. This value is then dec-
remented on the second active clock edge to arrive after the write (that is, after the fist complete period
of the clock). When the timer counter under-flows (reaches 0) the appropriate interrupt is asserted. The
timer counters can be read at any time. The clock source and mode are selectable by writing to various
bits in the System Control register (clock sources are 512 and 2 kHz).
The timer counters can operate in two modes: Free-running or Prescale.
1.2.12.1 Free-Running Mode
In Free-running mode, the counter wraps around to 0xFFFF when it under-flows and continues counting
down. Any value written to TC1 or TC2 is decremented on the second edge of the selected clock.
1.2.12.2 Prescale Mode
In Prescale mode, the value written to TC1 or TC2 is automatically reloaded when the counter under-
flows. Any value written to TC1 or TC2 is decremented on the second edge of the selected clock. This
mode can produce a programmable frequency to drive the buzzer or generate a periodic interrupt.
1.2.13 Realtime Clock
The CL-PS7110 contains a 32-bit RTC (realtime clock). The RTC can be written to and read from in the
same manner as the timer counters, but is 32 bits wide. The RTC is always clocked at 1 Hz and also con-
tains a 32-bit output-match register, which can be programmed to generate an interrupt when the time in
the RTC matches a specific time written to this register.
1.2.14 DC-to-DC Converter
Two programmable duty ratio 96-kHz clock outputs are provided by the CL-PS7110. These drives are to
be used as DC-to-DC converters in the PSU (power-supply unit) subsystem. These clocks are enabled
by external input pins that are normally connected to the output from comparators monitoring the DC-to-
DC converter output. The duty ratio (and hence the converter on-time) can be programmed from 1-in-16
May 1997
DATA BOOK v1.5
23
FUNCTIONAL DESCRIPTION
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