CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
3.2 Internal Registers
Table 3-2 shows all internal registers in the CL-PS7110. A 4-Kbyte segment of memory, in the range
8000.0000–8000.0FFF, is reserved for CL-PS7110 internal use. Accesses in this range do not cause any
external bus activity unless Debug mode is enabled. Writes to bits that are not explicitly defined in the
internal area are illegal, and have no effect. Reads from bits not explicitly defined in the internal area are
legal, but read undefined values. All the internal addresses can only be accessed as 32-bit words, and
are always on a word boundary (except for the PIA Port registers, which can be accessed as bytes).
Address bits in the range A0–A5 are not decoded. This means each internal register is valid for 64 bytes
(that is, the SYSFLG register appears at locations 8000.0140–8000.017C). The PIA Port registers are
byte-wide, but can be accessed as a word. These registers additionally decode A0 and A1. All addresses
are hexidecimal.
Table 3-2. Internal I/O Memory Locations
Address
8000.0000
8000.0001
8000.0002
8000.0003
8000.0040
8000.0041
8000.0042
8000.0043
8000.0080
8000.00C0
8000.0100
8000.0140
8000.0180
8000.01C0
8000.0200
8000.0240
8000.0280
8000.02C0
8000.0300
8000.0340
8000.0380
8000.03C0
Name
PADR
PBDR
PCDR
PDDR
PADDR
PBDDR
PCDDR
PDDDR
PEDR
PEDDR
SYSCON
SYSFLG
MEMCFG1
MEMCFG2
DRFPR
INTSR
INTMR
LCDCON
TC1D
TC2D
RTCDR
RTCMR
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RD
RW
RW
RW
RD
RW
RW
RW
RW
RW
RW
Size
Comments
8 Port A Data register
8 Port B Data register
8 Port C Data register
8 Port D Data register
8 Port A Data Direction register
8 Port B Data Direction register
8 Port C Data Direction register
8 Port D Data Direction register
4 Port E Data register
4 Port E Data Direction register
32 System Control register
32 System Status Flags register
32 Expansion and ROM Memory Configuration Register 1
32 Expansion and ROM Memory Configuration Register 2
8 DRAM Refresh Period register
16 Interrupt Status register
16 Interrupt Mask register
32 LCD Control register
16 Read/write data to TC1
16 Read/write data to TC2
32 Realtime Clock Data register
32 Realtime Clock Match register
40
PROGRAMMING INTERFACE
May 1997
DATA BOOK v1.5
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