CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 3-2. Internal I/O Memory Locations (cont.)
Address
8000.0400
8000.0440
8000.0480
8000.04C0
8000.0500
8000.0540
8000.0580
8000.05C0
8000.0600
8000.0640
8000.0680
8000.06C0
8000.0700
8000.0740
8000.0780
8000.07C0
8000.0800
8000.0840
8000.0880–BFFF.FFFF
Name
PMPCON
CODR
UARTDR
UBLCR
SYNCIO
PALLSW
PALMSW
STFCLR
BLEOI
MCEOI
TEOI
TC1EOI
TC2EOI
RTCEOI
UMSEOI
COEOI
HALT
STDBY
Reserved
R/W
RW
RW
RW
RW
RW
RW
RW
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
WR
–
Size
Comments
12 DC-to-DC Pump Control register
8 Codec Data I/O register
8 UART FIFO Data register
32 UART Bit Rate and Line Control register
16 Synchronous Serial I/O Data register
32 Least-significant 32-bit word of LCD Palette register
32 Most-significant 32-bit word of LCD Palette register
– Write to clear all start up reason flags
– Write to clear Battery Low interrupt
– Write to clear Media Changed interrupt
– Write to clear Tick and Watchdog interrupt
– Write to clear TC1 interrupt
– Write to clear TC2 interrupt
– Write to clear RTC Match interrupt
– Write to clear UART Modem Status Changed interrupt
– Write to clear Codec Sound interrupt
– Write to enter idle state
– Write to enter standby state
– Write has no effect; read is undefined
All internal registers in the CL-PS7110 are reset (cleared to ‘0’) by a system reset (NPOR, NRESET, or
NPWRFL become active), except for the DRAM Refresh Period register (DRFPR), which is only reset
when NPOR becomes active. In addition, the Realtime Clock Data register (RTCDR) and Realtime Clock
Match register (RTCMR) are never reset. This ensures that the DRAM contents and system time are pre-
served through a user reset or power-fail condition.
3.2.1 PADR — Port A Data Register
Values written to this 8-bit read/write register are output on the Port A pins if the corresponding data direc-
tion bits are set high (port output). Values read from this register reflect the external state of Port A, not
necessarily the value written to it. All bits are cleared by a system reset.
3.2.2 PBDR — Port B Data Register
Values written to this 8-bit read/write register are output on the Port B pins if the corresponding data direc-
tion bits are set high (port output). Values read from this register reflect the external state of Port B, not
necessarily the value written to it. All bits are cleared by a system reset.
May 1997
DATA BOOK v1.5
41
PROGRAMMING INTERFACE
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