CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 3-9. Values of the Random Access Wait State Field
Value
00
01
10
11
No. Wait
states
4
3
2
1
Required Random Access Speed (ns)
250
200
150
100
Table 3-10. Values of the Sequential Access Wait State Field
Value
00
01
10
11
No. Wait
States
3
2
1
0
Required Sequential Random Access
Speed (ns)
150
120
80
40
SQAEN
Sequential access enable. Setting this bit enables sequential accesses that are on a
quad-word boundary to take advantage of faster access times from devices that sup-
port Page mode. The sequential access is faulted after four words, (to allow video
refresh cycles to occur), even if the access is part of a longer sequential access.
CLKEN
Expansion clock enable. Setting this bit enables the EXPCLK to be active during
accesses to the selected expansion device. This provides a timing reference for
devices that need to extend bus cycles using the EXPRDY input. Back-to-back (but
not necessarily Page mode) accesses result in a continuous clock.
See Chapter 4 for more detail on bus timing.
3.2.15 DRFPR — DRAM Refresh Period Register
The DRAM Refresh Period register is an 8-bit read/write register that enables refresh and selects the
refresh period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the
DRAM refresh period register is only cleared by a power on reset, that is, the register state is maintained
during a power fail or user reset.
7
RFSHEN
RFSHEN
60
RFDIV
DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated
by the CL-PS7110 at a rate set by the RFDIV field. Setting this bit also enables Self-
refresh mode when the CL-PS7110 is in the standby state.
May 1997
DATA BOOK v1.5
49
PROGRAMMING INTERFACE
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