CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
CRXFE
CTXFF
SSIBUSY
BOOT8BIT
Reserved
VERID
Codec Rx FIFO empty bit. This is set if the 16-byte codec Rx FIFO is empty.
Codec Tx FIFO full bit. This is set if the 16-byte codec Tx FIFO is full.
Synchronous serial interface busy bit. This bit is set while data is shifted in or out of
the synchronous serial interface, when clear data is valid to read.
This bit indicates the default (power-on reset) bus width of the ROM interface. If set,
the initial bus width is 8 bits, if clear it is 32 bits. See Memory Configuration Register
1 for more details on the ROM interface bus width. The state of this bit is determined
by the state of Port E bit 0 during power-on reset. LOW during power-on reset clears
the BOOT8BIT bit and the system boots from a 32-bit ROM, HIGH during power-on
reset sets the BOOT8BIT bit and the system boots from a 8-bit ROM.
Write has no effect, always reads ‘0’.
Version ID bits. These two bits determine the version identification for the
CL-PS7110. Reads ‘0’ for the first version.
3.2.13 MEMCFG1 — Memory Configuration Register 1
Expansion and ROM space is selected by one of eight chip selects. Each chip select is active for 256
Mbytes and the timing and bus transfer width can be programmed individually. This is accomplished by
programming 8-byte-wide fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in
these registers are cleared by a system reset.
The Memory Configuration Register 1 is a 32-bit read/write register that sets the configuration of the four
expansion and ROM selects NCS0–NCS3. Each select is configured with a 1-byte field, starting with
expansion select 0.
31
24
NCS3 configuration
23
16
NCS2 configuration
15
8
NCS1 configuration
7
0
NCS0 configuration
3.2.14 MEMCFG2 — Memory Configuration Register 2
The Memory Configuration Register 2 is a 32-bit read/write register that sets the configuration of the four
expansion and ROM selects CS4–CS7. Each select is configured with a 1-byte field, starting with expan-
sion select 4.
31
24 23
16 15
CS7 configuration
CS6 configuration
CS5 configuration
87
0
CS4 configuration
Each of the eight byte fields in the Memory Configuration registers are identical and define the number of
wait states, the bus width, enable EXPCLK output during accesses and enable sequential mode access.
This byte field is defined below.
7
6
5
43
21
0
CLKEN
SQAEN
Sequential access wait state Random access wait state
Bus width
May 1997
DATA BOOK v1.5
47
PROGRAMMING INTERFACE
Share Link: 
