CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
RFDIV
This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a 128-
kHz clock and is given by the formula:
Frequency (kHz) = 128/(RFDIV + 1), that is,
RFDIV = (128/Refresh frequency (kHz)) − 1
Equation 3-1
The maximum refresh frequency is 64 kHz, the minimum is 1 kHz. The RFDIV field should not be pro-
grammed with ‘0’ as this results in no refresh cycles being initiated.
3.2.16 INTSR — Interrupt Status Register
The Interrupt Status register is a 16-bit read-only register. This register reflects the current state of the 16
interrupt sources within the CL-PS7110. Each bit is set if the appropriate interrupt is active. The interrupt
assignment is given below.
7
EINT3
15
SSEOTI
6
EINT2
14
UMSINT
5
EINT1
13
URXINT
4
CSINT
12
UTXINT
3
MCINT
11
TINT
2
WEINT
10
RTCMI
1
BLINT
9
TC2OI
0
EXTFIQ
8
TC1OI
EXTFIQ
BLINT
WEINT
MCINT
CSINT
EINT1
External fast interrupt. This interrupt is active if the NEXTFIQ input pin is forced low
and is mapped to the FIQ input on the ARM710A microprocessor.
Battery low interrupt. This interrupt is active if no external supply is present (BATOK
is high), and the battery-OK input pin BATOK is forced low. This interrupt is de-
glitched with a 16-kHz clock so it only generates an interrupt if it is active for longer
than 62.5 ms. It is mapped to the FIQ input on the ARM710A microprocessor and is
cleared by writing to the BLEOI location.
Watch dog expired interrupt. This interrupt is active on a rising edge of the periodic
64-Hz tick interrupt clock if the tick interrupt is still active, that is, if a tick interrupt has
not been serviced for a complete tick period. It is cleared by writing to the TEOI loca-
tion.
Media changed interrupt. This interrupt is active after a rising edge on the MEDCHG
input pin has been detected, This input is de-glitched with a 16-kHz clock and only
generates an interrupt if it is active for longer than 62.5 ms. It is mapped to the FIQ
input on the ARM710A microprocessor and is cleared by writing to the MCEOI loca-
tion.
Codec sound interrupt. This interrupt is active if the codec interface is enabled and
the codec data FIFO has reached half full or empty (depending on the interface direc-
tion). It is cleared by writing to the COEOI location.
External interrupt input 1. This interrupt is active if the NEINT1 input is active (low). It
is cleared by returning NEINT1 to the passive (high) state.
50
PROGRAMMING INTERFACE
May 1997
DATA BOOK v1.5
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