CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
extended by integer multiples of the clock period (54 ns), by either driving EXPRDY low and or by program-
ming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer,
if low at this point the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK
need not be referenced when driving EXPRDY but is shown for clarity.
2) Consecutive reads with sequential access enabled are identical except that the sequential access wait state
field is used to determine the number of wait states.
Consecutive expansion write cycles with minimum wait states
EXPCLK
NCS[3:0]
CS[7:4]
NMWE
A[27:0]
tEXWR
t8
tEXWR
t8
t24
WORD
t2
t7
t2
D[31:0]
BUS HELD
WRITE DATA
WRITE DATA
EXPRDY
t5
t6
Figure 4-2. Expansion and ROM Write Timing
NOTES:
1) tEXWR = 80 ns maximum for zero wait states. This time can be extended by integer multiples of the clock
period (54 ns), by either driving EXPRDY low and or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer, if low at this point the transfer is delayed by
one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY
but is shown for clarity.
2) Consecutive writes with sequential access enabled are identical except that the sequential access wait state
field is used to determine the number of wait states.
3) Zero wait states for sequential writes is not supported, one state automatically is added.
64
ELECTRICAL SPECIFICATIONS
May 1997
DATA BOOK v1.5
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