CL-PS7110
Low-Power System-on-a-Chip
CL2
CL1
t20
t15
t16
t17
t18
t19
t21
FRM
t22
M
t23
DD[3:0]
Figure 4-7. LCD Controller Timing
NOTES:
1) This diagram shows the end of a line.
2) If FRM is high during the CL1 pulse, this marks the first line in the display.
3) CL2 low time is doubled during the CL1 high pulse.
May 1997
DATA BOOK v1.5
69
ELECTRICAL SPECIFICATIONS