CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
WORD write followed by sequential word write to DRAM (MCLK shown for reference only)
MCLK
DRA[12:0]
RAS[3:0]
CAS[3:0]
D[31:0]
ROW COL
ROW
tRC
t9
tRAS
tRP
COL 1
t10
t12
tCAS
t11
COL 2
tCP
COL n
tPC
DATA OUT
t13
t14
DATA OUT 1
DATA OUT 2
DATA OUT n
NMOE
NMWE
WORD
WRITE
Figure 4-4. DRAM Write Cycles
NOTES:
1) tRC (Write cycle time) = 160 ns minimum at MCLK = 18.432 MHz
2) tRAC (Write access time from RAS) = 80 ns minimum at MCLK = 18.432 MHz
3) tRP (RAS precharge time) = 80 ns minimum at MCLK = 18.432 MHz
66
ELECTRICAL SPECIFICATIONS
May 1997
DATA BOOK v1.5
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