CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
4.6.5 High-Z (System) Test Mode
This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0.
This test mode asynchronously disables all output buffers on the CL-PS7110; this has the effect of remov-
ing the CL-PS7110 from the PCB so that other devices on the PCB can be tested. The internal state of
the CL-PS7110 is not altered directly by this test mode.
4.6.6 Test ROM Mode
This mode is entered by holding the MEDCHG input high during the transition from low to high of the
NPOR input pin. If Test ROM mode is enabled the processor boots from an alternative 8-bit test ROM.
The effect of this test mode is to reverse the decoding for all expansion selects. Table 4-7 shows this
decoding. In addition the sense of bit 1 in the Memory Configuration register is reversed so that 00 = 8-
bit access, Table 4-7 lists the chip select address ranges, and Table 4-8, the bus width field combinations
during Test ROM mode. This has the effect of making the boot ROM an 8-bit device connected to CS7.
Table 4-7. Chip Select Address Ranges During Test ROM Mode
Address Range
0000.0000–0FFF.FFFF
1000.0000–1FFF.FFFF
2000.0000–2FFF.FFFF
3000.0000–3FFF.FFFF
4000.0000–4FFF.FFFF
5000.0000–5FFF.FFFF
6000.0000–6FFF.FFFF
7000.0000–7FFF.FFFF
Expansion Chip Select in Test ROM Mode
CS7
CS6
CS5
CS4
NCS3
NCS2
NCS1
NCS0
Table 4-8. Expansion and ROM Interface Bus Width During Test ROM Mode
Bus Width Field in ROM Test Mode
Expansion Transfer Mode
00
8-bit-wide bus access
01
PCMCIA mode
10
32-bit-wide bus access
11
16-bit-wide bus access
May 1997
DATA BOOK v1.5
73
ELECTRICAL SPECIFICATIONS
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