CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
P
PCMCIA memory area 48
pin diagram 31
pin information
A[0–27] 32
ADCCLK 33
ADCIN 33
ADCOUT 33
BATOK 33
BUZ 34
CL[1–2] 34
COL[0–7] 34
CS[4–7] 32
CTS 33
D[0–31] 32
DCD 33
DD[0–3] 34
DRA[12–0] 32
DRIVE[0–1] 34
DSR 33
EINT[3] 32
EXPCLK 32
EXPRDY 32
FB[0–1] 34
FRM 34
LEDDRV 33
M 34
MEDCHG 32
MOSCIN/ MOSOUT 34
NADCCS 33
NBATCHG 33
NCAS[0–3] 32
NCS[0–3] 32
NEINT[1–2] 32
NEXTFIQ 32
NEXTPWR 33
NMOE 32
NMWE 32
NPOR 33
NPWRFL 33
NRAS[0–3] 32
NTEST[0–1] 34
numeric pin listing 35
NURESET 33
PA[0–7] 34
PB[0–7] 34
PC[0–7] 34
PCMCK 33
PCMIN 33
PCMOUT 33
PCMSYNC 33
PD[0–7] 34
80
INDEX
CL-PS7110
Low-Power System-on-a-Chip
PE[0–3] 34
PHDIN 33
RTCIN/ RTCOUT 34
RUN 33
RxD 33
SMPLCK 33
TxD 33
WAKEUP 33
WORD 32
WRITE 32
R
random access speed 49
random access wait state field 49
registers
BOOT8BIT Mode 18
DRAM Refresh Period 21, 29–30, 49
internal I/O memory locations table 40
Internal Mask. See ARM710A Data Sheet
Interrupt Mask 13, 40, 52
Interrupt Status 13, 50
See also ARM710A Data Sheet
LCD Control 21, 40, 52
Memory Configuration 73
Memory Configuration Register 1 18, 40, 47
Memory Configuration Register 2 47
Output Shift 21
programming interface 39–59
Pump Control 24, 41, 54
Realtime Clock Data 29, 40–41
Realtime Clock Match 53
System Control 23, 26, 40, 43
System Status Flags 21, 40, 45
UART Bit Rate and Line Control 23, 41, 46, 51, 55
UART Rx 13
resets, asynchronous 29–30
ROM 73
S
sequential access wait state field 49
sequential random access speed 49
signals
notional input 70
software-selectable test functionality 74
SPI 2, 12, 21, 45
T
timing
DRAM CAS-Before-RAS Refresh Cycle 68
DRAM Read Cycles 65
DRAM Write Cycles 66
Expansion and ROM Read 63
May 1997
DATA BOOK v1.5
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