CL10K30A View Datasheet(PDF) - Clear Logic
Part Name
Description
MFG CO.
'CL10K30A' PDF : 16 Pages View PDF
LIBERATOR CL10K30A
AC Electrical Specifications cont.
External Bi-Directional Timing Parameters[5]
Symbol
Parameter
tINSUBIDIR
Setup for Bi-directional Pins with Global
Clock at Adjacent LE Registers
tINHBIDIR
Hold Time for Bi-directional Pins with Global
Glock at Adjacent LE Registers
tOUTCOBIDIR
Clock-to-output Delay for Bi-directional Pins
with Global Clock at IOE Register
tXZBIDIR
Synchronous IOE Output Buffer Disable
Delay
tZXBIDIR
Synchronous IOE Output Buffer Disable
Delay, Slow Slew Rate = off
Speed: -1
Min Max
4.2
0.0
2.0
5.4
6.2
6.2
Speed: -2
Min Max
4.9
0.0
2.0
6.2
7.5
7.5
Speed: -3
Min Max Unit
6.8
ns
0.0
ns
2.0
8.3
ns
9.8
ns
9.8
ns
10KA tbl 12C
AC Test Conditions
(A)
VCCIO
OUTPUT
35 pF
Includes jig
capacitance
703 Ω
8.06k Ω
(B)
VCCIO
703 Ω
OUTPUT
5 pF
Includes jig
capacitance
8.06k Ω
All Input Pulses
3.0V
90%
GND 10%
≤ 3ns
A: Test fixture set-up A is for general testing.
B: Test fixture set-up B is for high Z testing (tZX#).
90%
10%
≤ 3ns
10KA drw 02
Notes to Tables
1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for
periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.
2. Device inputs may be driven before VCCINT and VCCIO are powered.
3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 ºC.
4. Guaranteed but not tested. Characterized initially, and after any design changes
which may affect these parameters.
5. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
Revision History
6. Use AC Test Conditions set-up B for these parameters.
20 Apr. 2000:
01 Dec. 2000:
04 Jan. 2001:
29 Mar. 2001:
Created new document
Updated package availability and additional literature available
Corrected table on AC Electrical Specifications
Added Pin Configuration for the FBGA 256-pin package
Page 14
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