CLRC632 View Datasheet(PDF) - NXP Semiconductors.
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Description
MFG CO.
'CLRC632' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.3.3 FIFO buffer status information
The microprocessor can get the following FIFO buffer status data:
• the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
• the FIFO buffer full warning: bit HiAlert
• the FIFO buffer empty warning: bit LoAlert
• the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The CLRC632 can generate an interrupt signal when:
• bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
• bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation 1:
HiAlert = 64 – FIFOLength WaterLevel
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation 2:
LoAlert = FIFOLength WaterLevel
(2)
9.3.4 FIFO buffer registers and flags
Table 18 shows the related FIFO buffer flags in alphabetic order.
Table 19. Associated FIFO buffer registers and flags
Flags
Register name
Bit
FIFOLength[6:0]
FIFOLength
6 to 0
FIFOOvfl
ErrorFlag
4
FlushFIFO
Control
0
HiAlert
PrimaryStatus
1
HiAlertIEn
InterruptEn
1
HiAlertIRq
InterruptRq
1
LoAlert
PrimaryStatus
0
LoAlertIEn
InterruptEn
0
LoAlertIRq
InterruptRq
0
WaterLevel[5:0]
FIFOLevel
5 to 0
Register address
04h
0Ah
09h
03h
06h
07h
03h
06h
07h
29h
9.4 Interrupt request system
The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 51) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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