CMX589AP4 View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'CMX589AP4' PDF : 21 Pages View PDF
High Speed GMSK Modem
2 Signal List
4
CMX589A PRELIMINARY INFORMATION
Pin No.
E2/D5/
D2/P4
1
2
Signal
XTAL
XTAL/CLOCK
3 ClkDivA
4 ClkDivB
5
Rx HOLD
6 RxDCacq
7 PLLacq
8 Rx PSAVE
9
VBIAS
10 Rx FB
11 Rx Signal In
12
VSS
13 DOC1
14 DOC2
15 BT
16 Tx Out
17 Tx Enable
18 Tx PSAVE
19 Tx Data
20 Rx Data
21 Rx CLK
22 Tx CLK
Type
Description
output The output of the on-chip clock oscillator.
input
input
input
The input to the on-chip Xtal oscillator. A Xtal, or externally derived
clock (fXTAL) pulse input should be connected here. If an externally
generated clock is to be used, it should be connected to this pin and the
XTAL pin left unconnected. Note: Operation without a suitable Xtal or
clock input may cause device damage.
Logic level inputs control the internal clock divider and therefore the
transmit and receive data rate. See Table 4.
Logic level inputs control the internal clock divider and therefore the
transmit and receive data rate. See Table 4.
input
input
input
input
input
power
A logic 0 applied to this input will freeze the Clock Extraction and Level
Measurement circuits unless they are in ‘Acquire’ mode.
A logic 1 applied to this input will set the RX Level Measurement circuitry
to the Acquire mode.
A logic 1 applied to this input will set the RX Clock Extraction circuitry to
the ‘Acquire’ mode. See Table 6.
A logic 1 applied to this input will powersave all receive circuits except
for RX CLK output (which will continue at the set bit-rate) and cause the
RX Data and RX S/N outputs to go to a logic 0.
The internal circuitry bias line, held at VDD/2. This pin must be bypassed
to VSS by a capacitor mounted close to the pin.
Output of the RX Input Amplifier.
Input to RX input amplifier.
Negative supply (GND).
output
input
input
input
output
output
Connections to the RX Level Measurement Circuitry. A capacitor should
be connected from each pin to VSS.
Connections to the RX Level Measurement Circuitry. A capacitor should
be connected from each pin to VSS.
A logic level to select the modem BT (the ratio of the TX Filter's -3dB
frequency to the Bit-Rate). A logic 1 = BT of 0.5 and a logic 0 = BT of
0.3.
Gaussian filtered TX output signal. In powersave mode the Tx Out pin is
a high impedance open.
A logic 1 applied to this input, enables the transmit data path, through
the TX Filter to the TX Out pin. A logic 0 will place the TX Out pin to
VBIAS via a high impedance.
A logic 1 applied to this input will powersave all transmit circuits except
for the TX Clock.
The logic level input for the data to be transmitted. This data should be
synchronous with TX CLK.
A logic level output carrying the received data, synchronous with
RX CLK.
A logic level clock output at the received data bit-rate.
output A logic level clock output at the transmit-data rate.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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