CMX589AP4 View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'CMX589AP4' PDF : 21 Pages View PDF
High Speed GMSK Modem
7
CMX589A PRELIMINARY INFORMATION
Data Rates
(kbps)
BT = 0.3
R1
C1
4
120k 680pF
4.8
100k 680pF
8
91k
470pF
9.6
91k
390pF
16
47k
470pF
19.2
100k 180pF
32
38.4 *
47k
47k
220pF
180pF
64 *
56k
100pF
80 *
128 *
144 *
160 *
176 *
192 *
* VDD 4.5V, external clock
BT = 0.5
R1
C1
120k 470pF
100k 470pF
120k 220pF
47k 470pF
91k 150pF
91k 120pF
47k 150pF
47k 120pF
51k 68pF
39k 68pF
82k 22pF
68k 22pF
62k 22pF
56k 22pF
51k 22pF
Table 3: Data Rate vs. BT and Selected External Component Values
Note: In all cases, the value of R1 should not be less than 20.0k, and that the calculated value of C1
includes calculated parasitic capacitance.
2. R3, R4 and C6 form the gain components for the RX Input signal. R3 should be chosen as required by
the signal input level.
3. For bit rate 64kbps, R4 = 100k. For bit rate > 64kbps, R4 = 10k.
4. The values chosen for C2 and C3 (including stray capacitance) should be suitable for the applied VDD
and the frequency of X1.
As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency.
At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less
than 2.0K falling to 150 at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins
must be minimized.
5. For bit rate 64kbps, C6 = 22pF. For bit rate > 64kbps, C6 =
1
e.g. for 128kbps,
3 bit rate 2 10k
C6 = 41.1pF.
6. C7 and C8 should both be .015F for a data rate of 8kbps, and inversely proportional to the data rate for
other data rates, e.g. 0.030F at 4kbps, 1800pF at 64kbps, 680pF at 192kbps.
7. The tolerance of C9 is not very critical because it primarily serves as a DC blocking capacitor.
8. The CMX589A can operate correctly with the Xtal/Clock frequencies between 1.0MHz and 8.2MHz
(VDD = 5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V). External clock frequencies up to 25.6MHz
(VDD 4.5V) are also supported. (See Table 4 for examples.) For best results, a crystal oscillator design
should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork
crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult
your crystal manufacturer. Operation of this device without a Xtal or Clock input may cause device
damage.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
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