CMX649 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX649' PDF : 50 Pages View PDF
ADM Codec
CMX649
6.2 CODEC Data Interface
Clock generation (internal clock - Master mode) non burst mode
Synchronous operation (external clock – Slave mode)
Max Frame length : limited by burst clock to bit rate ratio only
Burst_CLK frequency : 5MHz max
Data word length : 8 or 16 bits
SYNC Delay : 0 Burst CLKs
SYNC Length : 1 – (data word length – 1 ) Burst CLKs
Words (slots) per frame : 1
Slot start references (from SYNC)
Line
TX_DATA
RX_DATA
Directio
n
Output
Input
Start at
Clk
1
1
Data Transition
Edge
rise
rise
Transmission
Order
msb first
msb first
Data Word Length
and Byte Order
8 or 16 bits (m.s. byte first)
8 or 16 bits (m.s. byte first)
Tx and Rx clocks are tied together for burst mode. There is only one sync input.
SYNC
Sync_setup
75nS min
Rx_setup
75nS min
Rx_hold
75nS min
Sync_hold
75nS min
BURST CLOCK
70%
30%
RX DATA
7
6
5
4
3
2
1
0
7
6
TX DATA
Configure to tri-state or
drive between frames.
Tx_delay,
50nS max
7
6
5
4
3
2
1
0
7
6
Figure 13 Burst Interface Timing Diagram for Concatenated Byte Transfers
Notes for Figure 13:
• In this example Bit 7 is the most significant bit.
• Once started Rx and Tx data bits are continuously streaming so long as the SYNC pulse continues at
the PCM sample rate.
• Configuration options support some variations of this timing diagram, e.g. data word length, without
affecting the timing shown.
• The TX_DATA output may be high impedance between burst frames depending on bit 9 of CLK
SOURCE CONTROL Register ($73).
© 2003 CML Microsystems Plc
38
D/649/2
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