CMX882D6 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX882D6' PDF : 70 Pages View PDF
FRS Signalling Processor
CMX882
1.6 C-BUS Register Description
1.6.1 C-BUS Register Summary
C-BUS Write Only Registers
ADDR.
(hex)
$01
$B0
$B1
$B2
$B3
$C0
$C1
$C2
$C3
$C7
$C8
$CA
$CB
$CD
$CE
$CF
REGISTER
C-BUS RESET
ANALOGUE GAIN
SIGNAL ROUTING
AUXILIARY ADC THRESHOLDS
AUXILIARY ADC CONTROL
POWER DOWN CONTROL
MODE CONTROL
AUDIO & DEVICE ADDRESS CONTROL
TX TONE
MODEM CONTROL
PROGRAMMING REGISTER
TX DATA 1
XTCSS & TX DATA 2
AUDIO TONE
INTERRUPT MASK
RESERVED REGISTER ADDRESS
Word Size
(bits)
0
16
16
16
8
16
16
16
16
16
16
16
16
16
16
16
The C-BUS address $CF is allocated for production testing and must not be accessed in normal
operation.
C-BUS Read Only Registers
ADDR
(hex)
$B4
$C5
$C6
$C9
$CC
REGISTER
AUXILIARY ADC DATA
RX DATA 1
STATUS
XTCSS & RX DATA 2
TONE STATUS
Word Size
(bits)
8
16
16
16
16
Interrupt Operation
The CMX882 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and
the IRQ Mask bit (bit 15) are both set to ‘1’. The IRQ bit is set when the state of the interrupt flag bits in
the Status register change from a '0' to '1' and the corresponding mask bit(s) in the Interrupt Mask register
is(are) set.
All interrupt flag bits in the Status register except the Programming Flag (bit 0) are cleared and the
interrupt request is cleared following the command/address phase of a C-BUS read of the flag register.
The Programming Flag bit is set to '1' only when it is permissible to write a new word to the Programming
register.
2004 CML Microsystems Plc
35
D/882/7
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