CMX882D6 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX882D6' PDF : 70 Pages View PDF
FRS Signalling Processor
CMX882
1.6.6 $B3 AUXILIARY ADC CONTROL: 8-bit write-only
Bit:
7
6
5
4
3
2
1
0
Aux ADC i/p select
Conversion Interval
The ‘Conversion Interval’ (bits 5 to 0) defines the time between measurements whilst the Auxiliary ADC is
enabled. This allows the user to trade-off device power consumption with response time.
Auxiliary ADC power = 0.5mW/VDD(A)/conversion (approximate)
Conversion Interval = 20.8µs per LSB.
(approximate)
The user should set an interval to ensure that no part of a received signal is missed, so that the signal
type can be correctly identified. If using the Rx Auto start-up feature the recommended maximum
Conversion Interval is 125µs. The ‘Auxiliary ADC’ register must not be updated whilst the Aux ADC is
enabled.
The Aux ADC i/p select (bits 7 to 6) control the input to the Auxiliary ADC. Control is independent of the
Analogue i/p select bits and hence the Aux ADC can monitor any one of the 4 inputs independently.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Auxiliary ADC input from:
Signal monitor (Sig_Monitor i/p)
Input amplifier 2 (Input_2 i/p)
Microphone (MIC i/p)
Discriminator (DISC i/p)
1.6.7
Bit:
$C0 POWER DOWN CONTROL: 16-bit write-only
15
14
13
12
11
Input_2
MIC
Disc
Input
Output Fine
amp
amp
amp
Gain
Gain 1
10
Output Fine
Gain 2
9
O/P Coarse
Gain 1
8
O/P Coarse
Gain 2
Bit:
7
6
5
4
3
2
1
0
Audio
Output
BIAS
Signal
Prog Reg
Processing
Save
Xtal_N
Clock_Out_N
Enable
Aux ADC
Rx Auto
start-up
Bits 15 to 5 provide the power control of the specified blocks. If a bit is '1', the corresponding block is on,
else it is powered down. A C-BUS or Power up reset clears all bits in this register to '0'.
If bit 5 is '0' the internal signal processing blocks are reset and placed into a power-save mode.
Bit 4 should be set to a '1' if any of the program registers (1.6.20) have been programmed as this
prevents them being reset after a Rx Auto start-up or when the Signal Processing blocks come out of
power save. If bit 4 is set to '0' the program registers will be reset to the C-BUS or Power-up reset state
whenever the Signal Processing blocks come out of power save.
Bits 3 and 2 control the xtal clock circuit. The xtal circuit is powered down by setting bit 3 to '1'. Note:
The Clock/Xtal pin may be driven by an external clock source regardless of the setting of these bits. The
Clock_Out pin is disabled (held low) by setting bit 2 to ‘1’. After a Power-up or C-BUS reset bits 2 and 3
are cleared to ‘0’, so that both the xtal circuit and clock output are enabled.
Bit 1 controls the Auxiliary ADC. If set to '1' the Auxiliary ADC will generate interrupts in accordance with
the settings of the interrupt mask bits. If bit 1 is '0' the Auxiliary ADC is disabled and powered down.
Bit 0 controls Rx Auto start up. If bit 0 is set to '1' and the Aux ADC input rises above the ‘High
Threshold’ the device will automatically enter receive mode and initiate Rx signal type identification for
those signals enabled in the Mode register. The correct Aux ADC input, Rx signal routing and power
down bits must be set for automatic receive start up to operate, the mode control bits should be set to '00'
in this case. If bit 0 is cleared to '0' the CMX882 will not automatically start-up and it is up to the host to
respond to Aux ADC interrupts in this case. Bit 0 must be set to '0' whilst writing through register $C8 -
Programming Register.
2004 CML Microsystems Plc
39
D/882/7
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