CS42L52-CNZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42L52-CNZR

Low-power, Stereo CODEC w/ Headphone & Speaker Amps

Cirrus Logic 

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5/13/08

CS42L52

6.13.4 HP/Speaker De-emphasis

Configures a 15µs/50µs digital de-emphasis filter response on the headphone/line and speaker outputs.

DEEMPHASIS

0

1

Control Port Status

Disabled

Enabled

6.13.5 Digital Soft Ramp

Configures an incremental volume ramp from the current level to the new level at the specified rate.

DIGSFT

0

1

Ramp Rate:

Volume Changes

Do not occur with a soft ramp

Occur with a soft ramp

1/8 dB every LRCK cycle

Affected Digital Volume Controls

MSTxMUTE (“Master Playback Mute” on page 52),

HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),

ADCxVOL[7:0] (“ADCx Volume” on page 57),

AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),

PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),

MSTxVOL[7:0] (“Master Volume Control” on page 63),

HPxVOL[7:0] (“Headphone Volume Control” on page 63),

SPKxVOL[7:0] (“Speaker Volume Control” on page 64),

ALC and Limiter Attack/Release (page 66 to page 68)

Beep Volume (“Beep Volume” on page 61)

Notes:

1. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to

occur with a soft ramp only when bits 7 and 6 in register 29h are set to ‘00’b.

6.13.6 Digital Zero Cross

Configures when the signal level changes occur for the digital volume controls.

DIGZC

0

1

Volume Changes

Do not occur on a zero cross-

ing

Occur on a zero crossing

Affected Digital Volume Controls

MSTxMUTE (“Master Playback Mute” on page 52),

AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),

PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),

MSTxVOL[7:0] (“Master Volume Control” on page 63),

ALC and Limiter Attack/Release (page 66 to page 68)

Beep Volume (“Beep Volume” on page 61)

Notes:

1. If the signal does not encounter a zero crossing, the requested volume change will occur after a

timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).

2. The zero cross function is independently monitored and implemented for each channel.

3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is enabled.

4. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to

occur on a zero crossing only when bits 7 and 6 in register 29h are set to ‘00’b.

DS680F1

53

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