CS42L52 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L52' PDF : 82 Pages View PDF
5/13/08
CS42L52
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description. Unless otherwise specified, all “Reserved” bits must
maintain their default value.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
7
CHIPID4
6
CHIPID3
5
CHIPID2
4
CHIPID1
3
CHIPID0
2
REVID2
1
REVID1
0
REVID0
6.1.1
Chip I.D. (Read Only)
I.D. code for the CS42L52.
CHIPID[4:0]
11100
Device
CS42L52
6.1.2
Chip Revision (Read Only)
CS42L52 revision level.
REVID[2:0]
000
001
010
011
Revision Level
A0
A1
B0
B1
6.2 Power Control 1 (Address 02h)
7
PDN_CHRG
6
Reserved
5
Reserved
4
3
2
1
PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA
0
PDN
6.2.1
Power Down ADC Charge Pump
Configures the power state of the ADC charge pump.
PDN_CHRG
0
1
ADC Charge Pump Status
Powered Up
Powered Down
6.2.2
Power Down PGAx
Configures the power state of PGA channel x.
PDN_PGAx
0
1
Application
PGA Status
Powered Up (ONLY when the ADC or the analog passthru is used)
Powered Down
“Analog In to Analog Out Passthrough” on page 32
Notes:
1. The CS42L52 employs a clever scheme for controlling the power to the PGA when PASSTHRU
(“Passthrough Analog” on page 52) is enabled. Refer to the referenced application for more information.
2. This bit should be used in conjunction with ADCxSEL and PGAxSEL bits to determine the analog
42
DS680F1
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