CS43L21-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21-DNZR' PDF : 63 Pages View PDF
CS43L21
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS43L21 after each input byte is read and is input to the
CS43L21 from the microcontroller after each transmitted byte.
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
1 0 0 1 0 1 AD0 0
INCR 6 5 4 3 2 1 0
76
ACK
ACK
START
10
76
ACK
10
Figure 19. Control Port Timing, I²C Write
DATA +n
76 10
ACK
STOP
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1 DATA + n
1 0 0 1 0 1 AD0 0
INCR 6 5 4 3 2 1 0
1 0 0 1 0 1 AD0 1
70
7
0
7
0
START
ACK
ACK
START
ACK
ACK
NO
ACK STOP
Figure 20. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
34
DS723A1
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