CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
CS43L22
7.4.6
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
MCLKDIV2
0
1
Application:
MCLK signal into DAC
No divide
Divided by 2
“Serial Port Clocking” on page 29
Note: In Slave Mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 38) is disabled.
7.5 Interface Control 1 (Address 06h)
7
6
5
4
3
2
1
M/S
INV_SCLK Reserved
DSP
DACDIF1
DACDIF0
AWL1
0
AWL0
7.5.1
7.5.2
Master/Slave Mode
Configures the serial port I/O clocking.
M/S
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
SCLK Polarity
Configures the polarity of the SCLK signal.
INV_SCLK
0
1
SCLK Polarity
Not Inverted
Inverted
7.5.3 DSP Mode
Configures a data-packed interface format for the DAC.
DSP
0
1
Application:
DSP Mode
Disabled
Enabled
“DSP Mode” on page 31
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 41).
2. The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
7.5.4 DAC Interface Format
Configures the digital interface format for data on SDIN.
DACDIF[1:0]
00
01
10
11
Application:
DAC Interface Format
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified
Reserved
“Digital Interface Formats” on page 30
Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
page 41).
40
DS792F2
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