CS51313 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
CS51313
ON Semiconductor
'CS51313' PDF : 23 Pages View PDF
CS51313
offset voltage in order to disable switching on the GATE
drivers.
CS51313−BASED VCC(CORE) BUCK REGULATOR
DESIGN EXAMPLE
Step 1: Definition of the Design Specifications
In computer motherboard applications the input voltage
comes from the “silver box” power supply. 5.0 V ± 5.0% is
used for conversion to output voltage, and 12 V ± 5.0% is
used for the external NFET gate voltage and circuit bias. The
CPU VCC(CORE) tolerance can be affected by any or all of
the following reasons:
1.buck regulator output voltage setpoint accuracy;
2.output voltage change due to discharging or charging of
the bulk decoupling capacitors during a load current
transient;
3.output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors,
circuit traces, and vias;
4.output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide a
VCC(CORE) that will meet the specified tolerance at the
CPU’s inputs.
The designer must also ensure that the regulator
component junction temperatures are kept within the
manufacturer’s specified ratings at full load and maximum
ambient temperature. As computer motherboards become
increasingly complex, regulator size also becomes
important, as there is less space available for the CPU power
supply.
Step 2: Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
ǒ Ǔ DVOUT + DIOUT
ESL
Dt
)
ESR
)
tTR
COUT
where:
ΔIOUT / Δt = load current slew rate;
ΔIOUT = load transient;
Δt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors and
circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula
ESRMAX
+
DVESR
DIOUT
where ΔVESR = change in output voltage due to ESR
(assigned by the designer).
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula
Number
of
capacitors
+
ESRCAP
ESRMAX
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet);
ESRMAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
DVESR + DIOUT ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX
+
DVESL
DI
Dt
where:
ΔI/ΔT = load current slew rate (as high as 20 A/μs);
ΔVESL = change in output voltage due to ESL.
The actual maximum allowable ESL can be determined
by using the equation:
ESLMAX
+
Number
ESLCAP
of output capacitors
where ESLCAP = maximum ESL per capacitor (it is
estimated that a 10 × 12 mm Aluminum Electrolytic
capacitor has approximately 4.0 nH of package inductance).
The actual output voltage deviation due to the actual
maximum ESL can then be verified:
DVESL
+
ESLMAX
Dt
DI
The designer now must determine the change in output
voltage due to output capacitor discharge during the
transient:
DVCAP
+
DI DtTR
COUT
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