CS51313 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
CS51313
ON Semiconductor
'CS51313' PDF : 23 Pages View PDF
CS51313
The minimum inductance value for the input inductor is
therefore:
LIN
+
DV
(dIńdt)MAX
where:
LIN = input inductor value;
ΔV = voltage seen by the input inductor during a full load
swing;
(dI/dt)MAX = maximum allowable input current slew rate
(0.1 A/μs for a Pentium II power supply).
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2, a roll−off rate of —40 dB/dec, and a
corner frequency:
fC
+
1.0
2.0p ǸLC
where:
L = input inductor;
C = input capacitor(s).
Step 7: Selection of the Switching FET
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance; and 2) Its very
fast switching times. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of VGS, and
the faster the turn−on time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turn−on switching losses, 4) turn−off
switching losses, and 5) gate−transitions losses. The latter
three losses are proportional to frequency. For the
conducting power dissipation rms values of current and
resistance are used for true power calculations. The fast
switching speed of the MOSFET makes it indispensable for
high−frequency power supply applications. Not only are
switching power losses minimized, but also the maximum
usable switching frequency is considerably higher.
Switching time is independent of temperature. Also, at
higher frequencies, the use of smaller and lighter
components (transformer, filter choke, filter capacitor)
reduces overall component cost while using less space for
more efficient packaging at lower weight.
The MOSFET has purely capacitive input impedance. No
DC current is required. It is important to keep in mind the
drain current of the FET has a negative temperature
coefficient. Increase in temperature causes higher
on−resistance and greater leakage current. For switching
circuits, VDS(ON) should be low to minimize power
dissipation at a given ID, and VGS should be high to
accomplish this. MOSFET switching times are determined
by device capacitance, stray capacitance, and the impedance
of the gate drive circuit. Thus the gate driving circuit must
have high momentary peak current sourcing and sinking
capability for switching the MOSFET. The input
capacitance, output capacitance and reverse−transfer
capacitance also increase with increased device current
rating.
Two considerations complicate the task of estimating
switching times. First, since the magnitude of the input
capacitance, CISS, varies with VDS, the RC time constant
determined by the gate−drive impedance and CISS changes
during the switching cycle. Consequently, computation of
the rise time of the gate voltage by using a specific
gate−drive impedance and input capacitance yields only a
rough estimate. The second consideration is the effect of the
“Miller” capacitance, CRSS, which is referred to as CDG in
the following discussion. For example, when a device is on,
VDS(ON) is fairly small and VGS is about 12 V. CDG is
charged to VDS(ON) − VGS, which is a negative potential if
the drain is considered the positive electrode. When the
drain is “off,” CDG is charged to quite a different potential.
In this case the voltage across CDG is a positive value since
the potential from gate−to−source is near zero volts and VDS
is essentially the drain supply voltage. During turn−on and
turn−off, these large swings in gate−to−drain voltage tax the
current sourcing and sinking capabilities of the gate drive.
In addition to charging and discharging CGS, the gate drive
must also supply the displacement current required by
CDG(IGATE = CDG dVDG/dt). Unless the gate−drive
impedance is very low, the VGS waveform commonly
plateaus during rapid changes in the drain−to−source
voltage.
The most important aspect of FET performance is the
Static Drain−To−Source On−Resistance (RDS(ON)), which
effects regulator efficiency and FET thermal management
requirements. The On−Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On−Resistance also
increases. Its positive temperature coefficient is between
+0.6%/C and +0.85%/C. The higher the On−Resistance the
larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used. The
reference designs derive gate drive from the 12 V supply,
which is generally available in most computer systems and
utilizes logic level FETs.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
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