CS5373A-ISZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5373A-ISZ' PDF : 40 Pages View PDF
CS5373A
5. OPERATIONAL MODES
The CS5373A has seven operational modes
and one sleep mode selected by the MODE2,
MODE1, and MODE0 pins.
Modes of Operation
MODE
Selection [2:0]
Mode Description
0
0 0 0 Modulator: enabled.
DAC: sleep.
1
0 0 1 Modulator: enabled.
DAC: AC OUT and BUF outputs.
2
0 1 0 Modulator: enabled.
DAC: AC OUT only, BUF high-z.
3
0 1 1 Modulator: enabled.
DAC: AC BUF only, OUT high-z.
4
1 0 0 Modulator: enabled.
DAC: DC common mode output.
5
1 0 1 Modulator: enabled.
DAC: DC differential output.
6
1 1 0 Modulator: enabled.
DAC: AC common mode output.
7
1 1 1 Modulator: sleep.
DAC: sleep.
Table 2. Operational Modes
bit stream output, i.e. an 86% one’s density
has, on average, a ‘1’ value in 86 of every 100
output data bits. The MDATA output has a
nominal 50% one’s density for a mid-scale dif-
ferential input, approximately 86% one’s den-
sity for a positive full-scale input, and
approximately 14% one’s density for a nega-
tive full-scale input.
5.1.2 Modulator Decimated Output
When the CS5373A modulator operates with
the CS5378 digital filter, the final decimated,
24-bit, full-scale output code range depends if
digital offset correction is enabled. With digital
offset correction enabled, amplifier offset and
the modulator internal offset are removed from
the final conversion result.
Modulator
Differential Analog
Input Signal
> + (VREF + 5%)
+ VREF
0V
- VREF
> - (VREF + 5%)
CS5378 Digital Filter
Output Code
Offset
Corrected
+100 mV
Offset
Error Flag Possible
5D1420
60CD40
000000
03B920
A2EBE0
A6A500
Error Flag Possible
5.1 Modulator Mode
Modulator mode (MODE 0) enables the ∆Σ
modulator and disables the DAC AC and DC
test circuitry to save power. This mode is used
for normal sensor measurements after self-
tests are completed.
5.1.1 Modulator One’s Density
In modulator mode (and whenever the modu-
lator is enabled) the differential analog input
signal is converted to an oversampled ∆Σ seri-
al bit stream on the MDATA output, with a
one’s density proportional to the differential
amplitude of the analog input signal.
One’s density of the MDATA output is defined
as the ratio of ‘1’ bits to total bits in the serial
Table 3. Output Coding for the CS5373A
Modulator and CS5378 Digital Filter Combination
5.1.3 Modulator Synchronization
The modulator is designed to operate synchro-
nously with other modulators in a measure-
ment network, so a rising edge on the MSYNC
input resets the internal conversion state ma-
chine to synchronize analog sample timing.
MSYNC is automatically generated by the
CS5378 digital filter after receiving a synchro-
nization signal from the external system, and
is chip-to-chip accurate within ± 1 MCLK peri-
od.
22
DS703F1
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