CS5373A-ISZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5373A-ISZ' PDF : 40 Pages View PDF
CS5373A
VA+
0.1µF
0.1µF
VA+
2.5 V
VREF
VA-
INPUT FROM
CS3301A
CS3302A
AMPLIFIER
SENSOR
TEST OUTPUT
ELECTRONICS
TEST OUTPUT
10 Ω
100µF +
10nF
C0G
Route BUF as diff pair
Route OUT as diff pair
Route VREF as diff pair
VA+
VD
CAP+
CAP-
BUF+
MODE0
BUF-
MODE1
MODE2
OUT+
ATT0
OUT-
ATT1
CS5373A ATT2
VREF+
VREF-
TDATA
680 Ω
680 Ω
680 Ω
680 Ω
*Populate with 2 x 10nF or
1 x 22nF C0G or better.
20nF*
C0G
20nF*
C0G
INR+
INF+
INF-
INR-
VA-
MCLK
MSYNC
MDATA
MFLAG
GND
VA-
0.1µF
VD
CS5378
SIGNALS
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
TBSDATA
MCLK
MSYNC
MDATA
MFLAG
Figure 13. Digital Signals
6. DIGITAL SIGNALS
The CS5373A is designed to operate with the
CS5378 digital filter. The digital filter gener-
ates the master clock and synchronization sig-
nals (MCLK and MSYNC) while receiving back
the modulator one-bit ∆Σ conversion data
(MDATA) and over-range flag (MFLAG). It
also generates digital one-bit ∆Σ test bit
stream data for the test DAC (TDATA) and
controls GPIO pins to set the operational
mode (MODE) and attenuation (ATT).
6.1 MCLK Connection
The CS5378 digital filter generates the master
clock for CS5373A, typically 2.048 MHz, from
a synchronous CLK input from the external
system. By default, MCLK is disabled at reset
and is enabled by writing the digital filter CON-
FIG register. If MCLK is disabled during oper-
ation, the CS5373A will enter power down
after approximately 40 µS.
MCLK must have low in-band jitter to guaran-
tee full analog performance, requiring a crys-
tal- or VCXO-based system clock into the
digital filter. Clock jitter on the digital filter ex-
ternal CLK input directly translates to jitter on
MCLK.
6.2 MSYNC Connection
The CS5378 digital filter also provides a syn-
chronization signal to the CS5373A. The
MSYNC signal is generated following a rising
edge received on the digital filter SYNC input.
By default MSYNC generation is disabled at
reset and is enabled by writing to the digital fil-
ter CONFIG register.
The input SYNC signal to the CS5378 digital
filter sets a common reference time t0 for mea-
surement events, thereby synchronizing ana-
log sampling across a measurement network.
The timing accuracy of the received SYNC sig-
nal from node to node must be +/- 1 MCLK to
maximize the MSYNC analog sample syn-
chronization accuracy.
The CS5373A MSYNC input is rising-edge
triggered and resets the internal MCLK
counter/divider to guarantee synchronous op-
eration with other system devices. While the
MSYNC signal synchronizes the internal oper-
ation of the CS5373A, by default, it does not
synchronize the phase of the incoming encod-
ed digital test bit stream (TBS) sine wave un-
less enabled in the digital filter TBSCFG
register.
26
DS703F1
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