CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
Register 13: Line Control (LineCTL, Read/Write)
Address: PacketPage base + 0112h
F
E
WakeupEn LoRx
Squelch
D
2-part
DefDis
C
B
PolarityDis Mod
BackoffE
A
Route
Wakeup
9
Auto
AUI/10BT
8
AUIonly
7
6
SerTxON SerRxON
5-0
010011
LineCTL determines the configuration of the MAC engine and physical interface.
BIT NAME
5-0 010011
6
SerRxON
7
SerTxON
8
AUIonly
DESCRIPTION
These bits provide an internal address used by the CS8920A to identify this as the
Line Control Register.
When set, the receiver is enabled. When clear, no incoming packets pass through the
receiver. If SerRxON is cleared while a packet is being received, reception is completed
and no subsequent receive packets are allowed until SerRxON is set again.
When set, the transmitter is enabled. When clear, no transmissions are allowed. If
SerTxON is cleared while a packet is being transmitted, transmission is completed and
no subsequent packets are transmitted until SerTxON is set again.
Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to
the following: (Note that the 10BASE-T transmitter will be inactive even when selected
unless link pulses are detected or bit DisableLT (register 19, bit 7) is set.)
AUIonly (Bit 8)
AutoAUI/10BT (Bit 9)
Physical Interface
1
N/A
AUI
0
0
10BASE-T
0
1
Auto-Select
9
AutoAUI/10BT See AUIonly (Bit 8) description above.
A
RouteWakeup Determines action to be taken when a wakeup frame is seen and bit F is set
(WakeupEn=1). When RouteWakeup=1, the EWAKE pin and a programmable interrupt
will be asserted. If RouteWakeup=0, only the EWAKE pin will be asserted. This is the
default case.
B
ModBackoffE When clear, the ISO/IEC standard backoff algorithm is used (see Section 3.10). When
set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends
the backoff delay after each of the first three Tx collisions.)
C PolarityD
The 10BASE-T receiver automatically determines the polarity of the received signal at
(10Base-T,
the RXD+/RXD- input (see Section 3.12). When this bit is clear, the polarity is
only)
corrected, if necessary. When set, no effort is made to correct the polarity. This bit is
independent of the PolarityOK bit (Register 14, LineST, Bit C), which reports whether
the polarity is normal or reversed.
D 2-partDefDis Before a transmission can begin, the CS8920A follows a deferral procedure. With the 2-
partDefDis bit clear, the CS8920A uses the standard two-part deferral as defined in
ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the 2-partDefDis bit set, the two-part deferral
is disabled.
Continued on the next page.
62
DS238PP2
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