CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
Register 13: Line Control (LineCTL, Read/Write) continued
CS8920A
Address: PacketPage base + 0112h
BIT NAME
DESCRIPTION
E
LoRxSquelch When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the
(10Base-T,
ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6
only)
dB. This is useful for operating with "quiet" cables that are longer than 100 meters.
F
WakeUpEn When set, the wakeup enable bit forces the MAC to look at a special Magic Packet
frame and ignore all other incoming data. WakeUpEn also enables some special logic
to determine when the ISA bus drivers are to be on/off and what is done when the
Magic Packet frame is seen.
After reset, if no EEPROM is found by the CS8920A, the register has the following initial state. If an EEPROM is
found, the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 0011
Note: For Rev. B of the CS8920A, if autonegotiation is selected and two CS8920As are connected back to back
the auto AUI/10BT function does not work.
Register 14: Line Status (LineST, Read-only)
Address: PacketPage base + 0134h
F
E
D
C
B
CRS
PolarityOK
A
9
8
7
6
5-0
10BT
AUI
LinkOK
010100
LineST reports the status of the Ethernet physical interface.
BIT NAME
DESCRIPTION
5-0 010100
These bits provide an internal address used by the CS8920A to identify this as the
Line Status Register. When reading this register, these bits will be 010100, where the
LSB corresponds to Bit 0.
7
LinkOK
When set, the 10BASE-T link has not failed. When clear, the link has failed either
because the CS8920A has just come out of reset, or because the receiver has not
detected any activity (link pulses or received packets) for at least 50 ms.
8
AUI
When set, the CS8920A is using the AUI.
9
10BT
When set, the CS8920A is using the 10BASE-T interface.
C
PolarityOK
When set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is
correct. If clear, the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is
clear, then the polarity is automatically corrected, if needed. The PolarityOK status bit
shows the true state of the incoming polarity independent of the PolarityDis control bit.
When PolarityDis is clear and PolarityOK is clear, the receive polarity is inverted, and
corrected.
E
CRS
This bit tells the host the status of an incoming frame. If CRS is set, a frame is
currently being received. CRS remains asserted until the end of frame (EOF). At EOF,
CRS goes inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of
the recovered data.
This register’s initial state after reset is: 0X0X 00XX X001 0100
DS238PP2
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