CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
Register 19: Test Control (TestCTL, Read/Write)
F
E
D
C
B
A
9
Disable AUIloop ENDEC
Backoff
loop
TestCTL controls the diagnostic test modes of the CS8920A.
Address: PacketPage base + 0118h
8
7
6
DisableLT
5-0
011001
BIT NAME
5-0 011001
7
DisableLT
9
ENDECloop
A
AUIloop
B
Disable
Backoff
DESCRIPTION
These bits provide an internal address used by the CS8920A to identify this as the Test
Control Register.
When set, the 10BASE-T interface allows packet transmission and reception regardless
of the link status. DisableLT is used in conjunction with the LinkOK (Register 14,
LineST, Bit 7) as follows:
LinkOK
0
DisableLT
0
No packet transmission or reception
allowed. Transmitter sends link pulses.
X
1
DisableLT overrides LinkOK to allow
packet transmission and reception.
1
N/A
DisableLT has no meaning if LinkOK = 1.
Note that if the receiver is receiving no link pulses, then the 10BASE-T transmitter can
be active only if bit DisableLT is set.
When set, the CS8920A enters internal loopback mode where the internal Manchester
encoder output is connected to the decoder input. The 10BASE-T and AUI transmitters
and receivers are disabled. When clear, the CS8920A is configured for normal
operation.
When set, the CS8920A allows reception while transmitting. This facilitates loopback
tests for the AUI. When clear, the CS8920A is configured for normal AUI operation.
When set, the backoff algorithm is disabled. The CS8920A transmitter looks only for
completion of the inter-packet gap before starting transmission. When clear, the backoff
algorithm is used.
At reset, if no EEPROM is found by the CS8920A, the register has the following initial state. If an EEPROM is
found, the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 1001
68
DS238PP2
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