CS8952 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8952' PDF : 81 Pages View PDF
CS8952
BIT
NAME
2
Link Error Report
Enable
TYPE
Read/Write 0
RESET
1
Packet Error Report Read/Write 0
Enable
0
Code Error Report Read/Write 0
Enable
DESCRIPTION
When set, this bit causes link errors to be reported by
a value of 3h on RXD[3:0] and the assertion of
RX_ER. When clear, link errors are not reported
across the MII.
When set, this bit causes packet errors to be
reported by a value of 2h on RXD[3:0] and the asser-
tion of RX_ER. When clear, packet errors are not
reported across the MII.
When set, code errors are reported and transmitted
on RXD[3:0].
When clear, this bit enables the Code Error Report
values on RXD[3:0] as selected by the Code Error
Report Select bit and also causes the assertion of
TX_ER to transmit a HALT code group.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
57
DS206F1
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