CS8952 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8952' PDF : 81 Pages View PDF
CS8952
BIT
5
4:0
NAME
CIM Status
TYPE
RESET
Read Only 0
PHY Address Field Read/Write Reset to the val-
ues on the
PHYAD[4:0] pins.
DESCRIPTION
When clear, this bit indicates that a stable link con-
nection has been detected. When an unstable link is
detected and the Carrier Integrity Monitor Disable bit
in the PCS Sub-Layer Configuration Register
(address 17h) is clear, this bit is set and latched. It
will remain set until this register is read.
The value on pins PHYAD[4:0] are latched into this
field at power-up or reset. These bits define the PHY
address used by the management layer to address
the PHY. The external logic must know this address
in order to select this particular CS8952’s registers
individually via the MDIO and MDC pins.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
59
DS206F1
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