CS89712
Address Range
0000.0000–0FFF.FFFF
1000.0000–1FFF.FFFF
2000.0000–2FFF.FFFF
3000.0000–3FFF.FFFF
4000.0000–4FFF.FFFF
5000.0000–5FFF.FFFF
6000.0000–6FFF.FFFF
7000.0000–7FFF.FFFF
Chip Select
CS[7]
(Internal only)
CS[6]
(Internal only)
nCS[5]
nCS[4]
nCS[3]
nCS[2]
nCS[1]
nCS[0]
Table 11. Chip Select Address Ranges After Boot From
On-Chip Boot ROM
0xC000.0000 to 0xDFFF.FFFF is allocated to
SDRAM. The 1.5 GByte, less 8 kbytes for internal
registers, is not accessible in the CS89712. The
MMU should be programmed to generate an abort
exception for access to this area.
Internal peripherals are addressed through a set of
internal registers from address 0x8000.0000 to
0x8000.3FFF.
Table 12 shows how the 4-Gbyte address range of
the ARM720T processor (as configured within this
chip) is mapped. The memory map shown assumes
that two CL-PS6700 PC Card controllers are con-
nected. If this functionality is not required, then the
nCS[4] and nCS[5] memory is available. The exter-
nal boot ROM is not fully decoded (i.e., the boot
code will repeat within the 256 Mbyte space from
0x7000.0000 to 0x8000.0000).
When booted from on chip boot ROM, the SRAM
is fully decoded up to 128 kbytes. Access to any lo-
cation above this range will wrap within the range.
Address
0xF000.0000
0xE000.0000
0xD000.0000
0xC000.0000
0x8000.4000
0x8000.2000
0x8000.0000
0x7000.0000
0x6000.0000
0x5000.0000
0x4000.0000
0x3000.0000
0x2000.0000-0x2000.02FF
0x2000.0300-0x2000.030F
0x2000.0310-0x2FFF.FFFF
0x1000.0000
0x0000.0000
Contents
Reserved
Reserved
Reserved
SDRAM
Unused
Internal registers
Internal registers
Boot ROM (nCS[7])
SRAM (nCS[6])
PCMCIA-1 (nCS[5])
PCMCIA-0 (nCS[4])
Expansion (nCS[3])
Expansion (nCS[2])
Ethernet Port (on nCS[2])
Expansion (nCS[2]) cont.
ROM Bank 1 (nCS[1])
ROM Bank 0 (nCS[0])
Table 12. CS89712 Memory Map in External Boot Mode
Size
256 Mbytes
256 Mbytes
256 Mbytes
64 Mbytes
~1 Gbyte
8 kbytes
8 kbytes
128 bytes
48k bytes
4 x 64 Mbytes
4 x 64 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
256 Mbytes
22
DS502PP2