CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
SDRAM Address
Pins
A0.
A1.
A2.
A3.
A4.
A5.
A6.
A7.
A8.
A9.
A10.
A11.
A12.
BA0.
BA1.
CS89712 Pin Names
a27/dra0
a26/dra1
a25/dra2
a24/dra3
a23/dra4
a22/dra5
a21/dra6
a20/dra7
a19/dra8
a18/dra9
a17/dra10
a16/dra11
a15/dra12
a14/dra13
a13/dra14
Table 16. SDRAM Address Pin Connections
2.13 SDRAM Initialization
The SDRAM is initialized in the power-on se-
quence as follows:
1) To stabilize internal circuits when power is ap-
plied, a 200+ µs pause must precede any signal
toggling.
2) After the pause, all banks must be precharged
using the Precharge command (including the
precharge all banks command).
3) Once the precharge is complete, and the mini-
mum tRP is satisfied, the mode register can be
programmed. After the mode register set cycle,
tRSC (2 CLK minimum) pause must be satis-
fied as well. (Only required for NEC SDRAM)
4) Eight or more refresh cycles must be per-
formed.
2.14 CL-PS6700 PC Card Interface
Two of the expansion memory areas are dedicated
to supporting up to two CL-PS6700 PC Card con-
troller devices. These are selected by nCS4 and
nCS5 (must first be enabled by bits 5 and 6 of
SYSCON2). For efficient, low power operation,
both address and data are carried on the lower 16
bits of the CS89712 data bus. Accesses are initiated
by a write or read from the area of memory allocat-
ed for nCS4 or nCS5. The memory map within
each of these areas is segmented to allow different
types of PC Card accesses to take place, for at-
tribute, I/O, and common memory space. The CL-
PS6700 internal registers are memory mapped
within the address space as shown in Table 17.
Note: Due to the operating speed of the CL-PS6700,
this interface is supported only for a processor
speed of 18 MHz.
A complete description of the protocol and AC tim-
ing characteristics can be found in the CL-PS6700
data sheet. A transaction is initiated by an access to
the nCS4 or nCS5 area. The chip select is asserted,
and on the first clock, the upper 10 bits of the PC
Card address, along with 6 bits of size, space, and
slot information are put out onto the lower 16 bits
Access Type
Attribute
I/O
Common memory
CL-PS6700 registers
Addresses for CL-PS6700 Interface 1
0x4000.0000–0x43FF.FFFF
0x4400.0000–0x47FF.FFFF
0x4800.0000–0x4BFF.FFFF
0x4C00.0000–0x4FFF.FFFF
Addresses for CL-PS6700 Interface 2
0x5000.0000– 0x53FF.FFFF
0x5400.0000–0x57FF.FFFF
0x5800.0000–0x5BFF.FFFF
0x5C00.0000–0x5FFF.FFFF
Table 17. CL-PS6700 Memory Map
26
DS502PP2
Share Link: 
