CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
be posted successfully. While the PRDY signal is
de-asserted, the chip select to the CL-PS6700 will
be de-asserted and the main bus will be released so
that DMA transfers to the LCD controller can con-
tinue in the background.
In the case of a PC Card read, the PRDY signal
from the CL-PS6700 will be de-asserted until the
read data is ready. At this point, it will be reasserted
and the access will be completed in the same way
as for a register access. In the case of a byte access,
only one 16-bit data transfer will be required to
complete the access. While the PRDY signal is de-
asserted, the chip select to the CL-PS6700 will be
de-asserted, and the main bus will be released so
that DMA transfers to the LCD controller can con-
tinue in the background.
The CS89712 will re-arbitrate for the bus when the
PRDY signal is reasserted to indicate that the read
or write transaction can complete. The CPU will
stall until the PC Card access is completed.
A card read operation may be split into a request
cycle and a data cycle, or it may be combined into
a single request/data transfer cycle. This depends
on whether the requested data is available in the in-
ternal CL-PS6700 prefetch buffer.
The request portion of the cycle, for a card read, is
similar to the request phase for a card write (de-
scribed above). If the requested data is available in
the prefetch buffer, the CL-PS6700 asserts the
PRDY signal before the rising edge of the third
clock and the CS89712 continues the cycle to read
the data. Otherwise, the PRDY signal is de-assert-
ed, and the request cycle is stalled. The CS89712
may then allow the DMA address generator to gain
control of the bus, to allow LCD refreshes to con-
tinue. When the CL-PS6700 is ready with the data,
it asserts the PRDY signal. The CS89712 then arbi-
trates for the bus and, once the request is granted,
the suspended read cycle is resumed. The CS89712
resumes the cycle by asserting the appropriate chip
select, and data is transferred on the next two
clocks if a word read (one clock if a byte read).
There is no support within the CS89712 for detect-
ing time-outs. The CL-PS6700 device must be pro-
grammed to force the cycle to be completed (with
invalid data for a read) and then generate an inter-
rupt if a read or write access has timed out (i.e.,
RD_FAIL or WR_FAIL interrupt). The system
software can then determine which access was not
successfully completed by reading the status regis-
ters within the CL-PS6700.
The CL-PS6700 has support for DMA data trans-
fers. However, DMA is supported only by software
emulation because the DMA address generator
built into the CS89712 is dedicated to the LCD
controller interface. If DMA is enabled within the
CL-PS6700, it will assert its PDREQ signal to
make a DMA request. This can be connected to one
of the CS89712’s external interrupts and be used to
interrupt the CPU for servicing the DMA request.
Each of the CL-PS6700 devices can generate an in-
terrupt PIRQ. Since the PIRQ signal is an open
drain on the CL-PS6700 devices, two CL-PS6700
devices may be wired OR’ed to the same interrupt.
The circuit can then be connected to one of the
CS89712’s active low external interrupt sources.
On the receipt of an interrupt, the CPU can read the
interrupt status registers on the CL-PS6700 devices
to determine the cause of the interrupt.
All transactions are synchronized to the EXPCLK
output from the CS89712 in 18.432 MHz mode.
The EXPCLK should be permanently enabled, by
setting the EXCKEN bit in the SYSCON1 register,
when the CL-PS6700 is used. The reason for this is
that the PC Card interface and CL-PS6700 internal
write buffers need to be clocked after the CS89712
has completed its bus cycles.
A GPIO signal from the CS89712 can be connected
to the PSLEEP pin of the CL-PS6700 devices to al-
low them to be put into a power saving state before
the CS89712 enters the Standby State. It is essen-
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DS502PP2
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