CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
ceive (SDIN) pins. This is synchronously con-
trolled by either the PLL or the external clock.
These fixed frequencies pass through a program-
mable divider network which will create the appro-
priate values for SCLK, LRCLK, and MCLK for
the desired sample frequency. Examples of sample
frequencies are shown in Table 24. Register
DAI64Fs enables/disables the bit clock frequency
of 64 fs (and the other features as shown in Figure
7), but must be complemented by SYSCON3 bit 9
which will enable/disable 128 fs. To enable one
rate, you must disable the other.
2.17.2.2 DAI Frame Format
Each DAI frame is 128 bits long and comprises one
audio sample. Of this 128-bit frame, only 32 bits
are used for digital audio data. The remaining bits
are output as zeros. The LRCK signal is used as a
FEATURE
SYSCON3
DAIR (DAI)
DAI64 fs
SYSCON2
DAI –128 fs
DAISEL[3] (H) DAIEN[16] (H)
I2SF64[0] (L)
(X)
128Fs[9] (H)
DAI-64 fs
DAISEL[3] (H) DAIEN[16] (H)
I2SF64[0] (H)
(X)
128Fs[9] (L)
SSI2
DAISEL[3] (L)
DAIEN[16] (L)
(X)
SERSEL[0] (L)
CODEC
DAISEL[3] (L)
DAIEN[16] (L)
(X)
SERSEL[0] (H)
Table 23. Matrix for Programming the MUX
Note:
To connect the port to any of the 4 features shown above, a minimum software configuration shown in the
table above must be observed. Each register column contains the bit name (bit #) that must be cleared or
set for each feature as shown in the column. This table does not complete the programming for each of the
features, but allows access to the port only. The interrupt masks for these features will have to be
programmed as well.
128 fs
Audio Bit
Clock (MHz)
64 fs
Clock Source
Audio Bit
(MHz)
Clock (MHz)
Sample
Frequency (KHz)
128 fs Divisor
(AUDDIV)
64 fs Divisor
(AUDDIV)
1.0240
0.5120
73.728
8
36
72
1.4112
0.7056
11.2896
11.025
8
16
1.5360
0.7680
73.728
16
18
36
2.8224
1.4112
11.2896
22.025
4
8
3.0720
1.5360
73.728
24
12
24
4.0960
2.0480
73.728
32
9
18
5,6448
2.8224
11.2896
44.1
2
4
6.1440
3.0720
73.728
48
6
12
Table 24. Relationship between Audio Clocks / Clock Source / Sample Frequencies
34
DS502PP2
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