CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
PLL
(73.728MHz)
EXTCLK
(11.2896)
Programmable Divide
(AUDIV)
MUX
(AUDCLKSRC)
128(fs)
/2
256Fs
/32
DAI
7-bit
counter
fixed at 4
Audio
Sample
Frequency
(fs)
Audio
Data
FIFO
Control
Audio Bit Clock 128/64(fs) SCLK
LRCLK(Fs)
MCLK
BUZZ
BUZZ-PIN
Figure 7. Digital Audio Clock Generation
LRCK
SCLK
SDATA O
SDATAI
Left Channel
128 SCLKs
Right Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Figure 8. CS89712 - Digital Audio Interface Timing – MSB / Left Justified format
frame synchronization. Each transition of LRCK
delineates the left and right halves of an audio sam-
ple. When LRCK transitions from high-to-low the
next 16 bits make up the right side of a sample.
When LRCK transitions from low-to-high the next
16 bits make up the left side of a sample.
2.17.2.3 DAI Signals
MCLK is used as an input to the CS89712 for gen-
erating the DAI timing. This signal is also usually
used as an input to a DAC/ADC as an oversampled
clock. This signal is fixed at 256 times the audio
sample frequency.
The SCLKbit clock is used as the bit clock input
into the DAC/ADC. This signal is fixed at 128 or
64 times the audio sample frequency.
LRCK is used as a frame synchronization input to
the DAC/ADC. This signal is fixed at the audio
sample frequency. This signal is clocked out on the
negative going edge of SCLK.
SDOUT is used for sending playback data to a
DAC. This signal is clocked out on the negative go-
ing edge of the SCLK output.
SDIN is used for receiving record data from an
ADC. This signal is latched by the CS89712 on the
positive going edge of SCLK.
DS502PP2
35
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