CS89712 View Datasheet(PDF) - Cirrus Logic
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MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
2.17.4.1 Read Back of Residual Data
All writes to the transmit FIFO must be in half-
words (i.e., in units of two bytes at a time). On the
receive side, it is possible that an odd number of
bytes will be received. Bytes are always loaded into
the receive FIFO in pairs. Consequently, in the case
of a single residual byte remaining at the end of a
transmission, it will be necessary to read the byte
separately. This is done by reading the status of two
bits in the SYSFLG2 register to determine the va-
lidity of the residual data. These two bits (RES-
VAL, RESFRM) are both set high when a residual
is valid. RESVAL is cleared on either a new trans-
mission or on reading of the residual bit by soft-
ware. RESFRM is cleared only on a new
transmission. By popping the residual byte into the
RX FIFO and then reading the status of these bits it
is possible to determine if a residual bit has been
correctly read.
Figure 10 illustrates this procedure. The sequence
is as follows: read the RESVAL bit, if this is a 0, no
action needs to be taken. If this is a 1, then pop the
residual byte into the FIFO by writing to the
SS2POP location. Then read back the two status
bits RESVAL and RESFRM. If these bits read back
01, then the residual byte popped into the FIFO is
valid and can be read back from the SS2DR regis-
ter. If the bits are not 01, then there has been anoth-
er transmission received since the residual read
procedure has been started. The data item that has
been popped to the top of the FIFO will be invalid
and should be ignored. In this case, the correct byte
will have been stored in the most significant byte of
the next half-word to be clocked into the FIFO.
Note: All the writes / reads to the FIFO are done word
at a time (data on the lower 16 bits is valid and
upper 16 bits are ignored).
Software manually pops the residual byte into the
RX FIFO by writing to the SS2POP location (the
value written is ignored). This write will strobe the
RX FIFO write signal, causing the residual byte to
be written into the FIFO.
2.17.4.2 Support for Asymmetric Traffic
The interface supports asymmetric traffic (i.e., un-
balanced data flow). This is accomplished through
separate transmit and receive frame sync control
lines. In operation, the receiving node receives a
byte of data on the eight clocks following the asser-
tion of the receive frame sync control line. In a sim-
ilar fashion, the sending node can transmit a byte of
data on the eight clocks following the assertion of
the transmit frame sync pulse. There is no correla-
tion in the frequency of assertions of the RX and
TX frame sync control lines (SSITXFR and
SSIRXFR). Hence, the RX path may bear a greater
data throughput than the TX path, or vice versa.
Residual bit valid
00
11
New RX byte received
New RX byte
received
01
Pop FIFO
Figure 10. Residual Byte Reading
38
DS502PP2
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