CSR8615A04-IQQF-R View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'CSR8615A04-IQQF-R' PDF : 114 Pages View PDF
Symbol
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode: input)
64
-
(a)
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
(b)
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
3 tsclkh
PCM_CLK high time
200
-
-
6, 201 thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ber 1 tsusclksynch
Set-up time for PCM_SYNC high to PCM_CLK low 20
-
-
y, Septem tdpout
Delay time from PCM_SYNC or PCM_CLK,
whichever is later, to valid PCM_OUT data (Long
-
Frame Sync only)
-
20
onda tdsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
15
.com.cn - M tdpoutz
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_OUT data line high
-
impedance
-
15
omm tsupinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
chec thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
o - apa Table 9.7: PCM Slave Timing
sa (a) Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
Prepared for james T (b) Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK
ns
ns
ns
ns
ns
ns
ns
ns
Pre-production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 55 of 114
CS-303726-DSP3
www.csr.com
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