CSR8615A04-IQQF-R View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'CSR8615A04-IQQF-R' PDF : 114 Pages View PDF
â– Generating these signals by DDS from CSR8615 QFN internal 4MHz clock. Using this mode limits
PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
â– Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of
frequencies to be generated with low jitter but consumes more power. To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
PSKEY_PCM_USE_LOW_JITTER_MODE sets the low jitter mode when the sync rate is 8kHz and the PCM clock
is set either by PSKEY_PCM_CLOCK_RATE or through the audio API, see BlueCore Audio API Specification.
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© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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