CY7C1346F View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY7C1346F' PDF : 16 Pages View PDF
Switching Characteristics Over the Operating Range (continued)[11, 12]
Parameter
tWES
tDS
tCES
Hold Times
tAH
tADH
tADVH
tWEH
tDH
tCEH
Description
GW, BWE, BW[A:D] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Address Hold after CLK Rise
ADSP , ADSC Hold after CLK Rise
ADV Hold after CLK Rise
GW,BWE, BW[A:D] Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
166 MHz
Min. Max.
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133 MHz
Min. Max.
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
CY7C1346F
100 MHz
Min. Max. Unit
1.5
ns
1.5
ns
1.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
0.5
ns
Document #: 38-05384 Rev. *B
Page 10 of 16
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