CY7C1346F
Truth Table [2, 3, 4, 5, 6, 7]
Next Cycle
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None H X X L X
L
X
X X L-H three-state
None L L X L L
X
X
X X L-H three-state
None L X H L L
X
X
X X L-H three-state
None L L X L H
L
X
X X L-H three-state
None L X H L H
L
X
X X L-H three-state
None X X X H X
X
X
X X X three-state
External L H L L L
X
X
X L L-H
Q
External L H L L L
X
X
X H L-H three-state
External L H L L H
L
X
L X L-H
D
External L H L L H
L
X
H L L-H
Q
External L H L L H
L
X
H H L-H three-state
Next
X X XL H
H
L
H L L-H
Q
Next
X X XL H
H
L
H H L-H three-state
Next
H X XL X
H
L
H L L-H
Q
Next
H X XL X
H
L
H H L-H three-state
Next
X X XL H
H
L
L X L-H
D
Next
H X XL X
H
L
L X L-H
D
Current X X X L H
H
H
H L L-H
Q
Current X X X L H
H
H
H H L-H three-state
Current H X X L X
H
H
H L L-H
Q
Current H X X L X
H
H
H H L-H three-state
Current X X X L H
H
H
L X L-H
D
Current H X X L X
H
H
L X L-H
D
Truth Table for Read/Write[2, 3]
Read
Function
GW
BWE
BWD
BWC
BWB
BWA
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA )
Write Byte B – (DQB and DQPB )
Write Bytes B, A
H
L
H
H
H
L
H
L
H
H
L
H
H
L
H
H
L
L
Write Byte C – (DQC and DQPC )
Write Bytes C, A
H
L
H
L
H
H
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD )
H
L
L
H
H
H
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD),BWE, GW = H..
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05384 Rev. *B
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