CY7C1346F View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY7C1346F' PDF : 16 Pages View PDF
CY7C1346F
Pin Definitions
Name
TQFP
I/O
Description
A0, A1 , A
37,36,32,
33,34,35,
36,37,44,
45,46,47,
48,49,81,
82 99,100
Input-
Address Inputs used to select one of the 64K address locations. Sampled
Synchronous at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A1, A0 feed the 2-bit counter.
BWA, BWB
BWC, BWD
GW
BWE
93,94,95, 96
88
87
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte
Synchronous Writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising
Synchronous edge of CLK, a global Write is conducted (ALL bytes are written, regardless of
the values on BW[A:D] and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a Byte Write.
CLK
89
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
98
CE2
97
CE3
92
OE
86
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
Synchronous in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored
if CE1 is HIGH.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
Synchronous in conjunction with CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
Synchronous in conjunction with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of
Asynchronous the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during
the first clock of a Read cycle when emerging from a deselected state.
ADV
83
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted, it automatically increments the address in a burst cycle.
ADSP
84
ADSC
85
ZZ
64
Input-
Synchronous
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, A is captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, A is captured in the address registers. A1, A0 are
also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
Input-
ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQA, DQB 52,53,56,57,
DQC, DQD, 58,59,62,63,
DQPA, DQPB, 68, 69,72,73,
DQPC,DQPD 74,75,78,79,
2,3,6,7,8,9,
12,13,18,19,
22,23,24,25,
28,29,51,
80,1,30
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by “A” during the previous clock rise
of the Read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
VDD
15,41,65,
Power Supply Power supply inputs to the core of the device.
91
Document #: 38-05384 Rev. *B
Page 3 of 16
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